The present invention relates generally to digital integrated circuits and, more particularly, to an apparatus for improved delay voltage level shifting for large voltage differentials.
Over the last several years, CMOS-based (complementary metal-oxide semiconductor) integrated circuit (IC) technologies have been designed to operate with progressively lower power supply voltages with each passing generation. Lower supply voltages dictate lower voltage swings for the associated digital signals, which typically switch between ground and the power supply voltage. The benefits of using lower supply voltages include lower power consumption and faster signal switching times. On the other hand, lower supply voltages also result in lower noise margins. CMOS logic IC power supply voltages currently available include, for example, 3.3 V, 2.5 V, 1.8 V, 1.5 V and 1.0 V. Depending on the application, a mix of the various CMOS technologies may be used in any particular electronic product, thus necessitating the use of digital voltage level shifters to translate CMOS signals generated using one power supply voltage to signals based on a different voltage level.
FIG. 1 is a schematic diagram of an existing CMOS voltage level shifter 100 used to translate lower voltage signals (e.g., 1.0 V) to higher voltage signals (e.g., 3.3 V). As is shown, the level shifter includes four FETs, NFETs T1 and T2, as well as PFETs T3 and T4. The FETs of level shifter 100 are typically thick oxide devices, as the thin oxide devices used for 1.0 V signals cannot operate at the higher 3.3 V operating voltage. The input signals A and ABAR represent lower voltage signals and drive the gates of NFETs T1 and T2, respectively. Signal ABAR is the logical complement (NOT) of signal A. As also illustrated, the source terminals of NFET T1 and NFET T2 are connected to ground, while the source terminals of PFET T3 and PFET T4 are connected to the higher voltage supply (e.g., 3.3 V). The gate terminals of T3 and T4 are cross-coupled to the respective drain terminals thereof. The drain terminal of T3 is further connected to the drain terminal of T1, while the drain terminal of T4 is connected to the drain terminal of T2. The output signal Z represents the voltage level shifted value of input signal A.
For example, if A is logical 1 at the lower operating voltage (e.g., 1.0 V) and ABAR is logical 0 (ground), then Z is logical 1 at the shifted, higher operating voltage (e.g., 3.3 V). In this case, the 1.0 V input at A renders NFET T1 conductive, while the 0 V input at ABAR leaves NFET T2 off. As a result, the gate voltage of PFET T4 is pulled to ground, rendering it conductive. Accordingly the gate of T3 (and therefore output Z) is pulled up to the higher operating voltage, which also leaves PFET T3 non-conducting. Conversely, if A is at 0 V and ABAR is at 1.0 V, then NFET T1 is switched off while NFET T2 is switched on. The gate of PFET T3 is pulled toward ground, thereby switching it on, which in turn causes the gate voltage of PFET T4 to rise and thus switch it off. Conductive NFET N2 can then pull the output voltage at Z all the way to ground, unopposed by T4. When operating properly, CMOS level shifter 100 does not draw DC current.
However, the conventional level shifter 100 of FIG. 1 typically requires large NFET to PFET ratios for proper operation, which is unlike most CMOS circuits that usually require the PFET device to be larger than the NFETs to achieve a balanced output rise and fall delay. When translating low voltage CMOS signals typical in CMOS technologies of gate lengths below 0.18 μm to higher voltage signals, the NFET to PFET size ratio required by the circuit in FIG. 1 can be as large as 60:1 or sometimes as large 100:1. Such ratios are required in order to achieve proper operation over process variations, voltage variations, and temperature variations (PVT). More specifically, the large NFET versus PFET ratio is required because the low voltage signals driving the gates of NFETs T1 and T2 are very close to the Vt (threshold voltage) of these devices and therefore are not able to turn T1 and T2 on strongly. The gates of PFETs T3 and T4, on the other hand, are driven by the higher voltage signal (e.g., 3.3 V). Thus, when these devices are turned on, they are strongly turned on. As a result, PFETs T3 and T4 must be very small relative to NFETs T1 and T2 so as to balance the current drive capability of the PFETs versus the NFETs.
The requirement for this level shifting circuit to operate over large process, voltage, and temperature ranges further pushes the NFET to PFET ratio even larger for conditions where the low voltage is at its lower tolerance value, the high voltage is at its higher tolerance value, and where the chip manufacturing process has resulted in strong PFETs and weak NFETs. Because NFETs T1 and T2 are so large, the A and ABAR inputs must drive a large gate capacitance. These high ratios can also make PFET T4 very weak relative with respect to NFET T2 for many PVT conditions, such as when the manufacturing process has created weak PFETs and strong NFETs and when the lower voltage supply is at its higher tolerance value. Under these conditions, the circuit of FIG. 1 has both a large output rise delay and a large output rise delay to output fall delay mismatch. Even under nominal PVT conditions, the large gate input capacitance and weak PFET create a slow circuit and large rise/fall delay mismatches, both of which are undesirable.
Accordingly, there is a need for an improved CMOS level shifting device which overcomes the above described disadvantages and allows for smaller NFET devices, improved rise/fall delays and improved rise/fall delay mismatch characteristics, and which operates correctly over extreme PVT variations.